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課程名稱 |
數位系統設計
Digital System Design |
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開課學期 |
99-2 |
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授課對象 |
電機資訊學院 電機工程學系 |
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授課教師 |
吳安宇 |
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課號 |
EE4041 |
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課程識別碼 |
901 43500 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期三6,7,8(13:20~16:20) |
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上課地點 |
電二146 |
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備註 |
總人數上限：40人 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Digital System Design Introduction
Fundamentals of Hardware Description Language
Logic Design at Register Transfer Level
Logic Design with Behavior Coding, Design Validation
Synthesizable Coding of Verilog
Coding Style and Verification Tool
Synthesis Tool Usage
Complexity Management and Performance Improvement
Implementation Project: MIPS Processor |
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課程目標 |
Basics:
Basic overview of digital systems
Front-end cell-based design flow, theory & practice
Refinement and improvement issues for digital systems
Presentation:
Implementation project
Peer competetion for advanced design features
Oral presentation |
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課程要求 |
Prerequisite:
Switch circuits and logic designs
Electronics
Grading:
CAD Labs and Homework 34%
Midterm Exam 28%
Final Project 30%
Impression (Attendance and Attitude) 8%
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
Textbook： Main:
Course slides.
For reference:
"Advanced Digital Design with the Verilog HDL," by M. D. Ciletti, Prentice Hall, 2003. |
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評量方式
(僅供參考) |
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